I. Industry Changes: Chain Reactions Triggered by Power-Device Upgrades

Over the past decade, power devices for PV inverters have undergone a profound generational shift: traditional Si IGBTs are being rapidly replaced by SiC MOSFETs. The driving force behind this transition is straightforward — the switching loss of SiC devices can drop to around 30 % of that of IGBTs, with virtually no reverse-recovery tail current. This pushes the switching frequency from 8–20 kHz in the IGBT era all the way up to 50–100 kHz or even higher.

Higher switching frequency brings comprehensive benefits:

• Miniaturized magnetic components: the volume of inductors and transformers is approximately inversely proportional to switching frequency. At 100 kHz, the size of filter inductors is only a fraction of that at 16 kHz, greatly boosting overall power density.

• Reduced filter burden: higher switching frequency shifts harmonics to higher-frequency bands. LCL filters can be made more compact, and total harmonic distortion (THD) of output current can be easily suppressed below 3 %.

• Improved efficiency: low switching losses of SiC plus high-frequency miniaturization push the peak efficiency of string inverters generally above 99 %.

Meanwhile, next-generation power-electronic equipment represented by Solid-State Transformers (SSTs) is moving out of laboratories into demonstration deployments. SSTs adopt a three-stage architecture: AC/DC rectifier stage + DAB high-frequency isolation stage + DC/AC inverter stage, operating at 50–200 kHz and replacing bulky line-frequency transformers with high-frequency transformers. If PV inverters constitute the primary battlefield for SiC, SSTs represent the end-state form of fully high-frequency power conversion.

Nevertheless, device upgrade is far more than simply "swapping power switches". Every doubling of switching frequency doubles system requirements for control loops and current sensing — this is the core contradiction discussed in this article.

II. SiC Solutions from Mainstream Vendors: What Parameters Tell Us

To understand why sensors must be upgraded, let us first examine how leading-vendor devices have pushed inverter performance.

2.1 Infineon CoolSiC™

Infineon’s CoolSiC™ 1200 V portfolio covers both modules and discrete components. Take the discrete device IMBG120R030M1H (CoolSiC G1 trench-type, TO-263-7 package) targeted for string inverters: 1200 V / 56 A with RDS(on) of merely 30 mΩ, total gate charge QG ≈ 63 nC, and datasheet-specified short-circuit withstand time of 3 μs. The new-generation CoolSiC G2 further reduces short-circuit withstand time to 2 μs while permitting maximum overload junction temperature up to 200 °C. On the module side, packages such as EasyPACK™ / Easy 2C offer half-bridge, three-level, Boost and other topologies, widely adopted for MPPT and inverter stages in string inverters.

2.2 onsemi EliteSiC

onsemi’s EliteSiC M3S planar 1200 V series is optimized for PV and energy-storage applications. Take NTH4L040N120M3S: 1200 V / 54 A, RDS(on)=40 mΩ, TO-247-4L package with Kelvin-source terminal, total gate charge QG(tot) as low as 75 nC and output capacitance Coss only 80 pF. Low Qg and low Coss are critical enablers for 100 kHz-class high-frequency switching. For modules, EliteSiC power-integrated modules in F1/F2 packages support boost, half-bridge, full-bridge and three-level topologies.

2.3 Sensing Requirements Derived from Device Parameters

Translating these device parameters into current-sensing requirements yields clear logic:

It can be observed that every key parameter of SiC devices translates directly into specifications for current sensors: MHz-level bandwidth, microsecond-scale response, and strong common-mode immunity. These three metrics have evolved from nice-to-have features into hard constraints for SiC-based inverter design.

III. Hardware Teardown: Physical Placement of Sensors on Inverter Layout

Theory means less than real-world hardware. The photo below shows a typical PV-inverter power-board teardown with physical layout of functional blocks clearly visible.

Notice the "Hall-effect current-measurement sensor" annotated in the figure. It sits adjacent to DC-input terminals and boost inductor within the Boost power loop. Another teardown photo of a string inverter is shown below.

Two categories of magnetic sensors are present in this unit: Hall-effect current sensors on the output side (for grid-tied current inner-loop feedback and overcurrent protection), plus residual-current-monitoring-unit (RCMU) sensors detecting ground residual current to satisfy PV safety standards. Summarizing typical layout positions of current sensors in inverters:

1. MPPT / Boost-stage inductor loop: sensor inserted between boost inductor and DC-link capacitor, measuring inductor current for average-current-mode control and MPPT power calculation. Layout placed close to inductors and power switches to shorten high-di/dt loops.

2. DC-link inlet: monitors DC-link current for power calculation and anomaly detection.

3. Inverter-bridge output (before LCL filter): primary feedback point for grid-tied current inner loop; one sensor per phase. Sensor output traces must keep away from switching nodes of bridge arms (high dv/dt noise sources). Sensors based on differential/gradient-sensing principles are preferred to suppress crosstalk.

4. AC output port: RCMU residual-current detection; all phase conductors pass through the magnetic core.

The core layout principle can be summarized concisely: sample current at points where current information remains complete (inside switching loops, before filters), while keeping electrically distant from strongest noise sources (bridge-arm mid-points). As SiC pushes dv/dt toward 100 V/ns, anti-interference design described in point 3 has become a major headache for layout engineers. This directly drives fast adoption of stray-field-immune solutions such as core-free differential Hall and TMR sensors.

IV. Current-Sensing from Topology Perspective: Buck-Boost and H-Bridge

From a principle standpoint, a typical string-PV-inverter power chain follows: MPPT stage (Boost or four-switch Buck-Boost) + DC-link + single-/three-phase inverter bridge.

In the MPPT stage, the four-switch Buck-Boost topology enables seamless transition between boost and buck operation under wide PV-voltage fluctuations (200–1500 V), stabilizing DC-link voltage at the optimal operating point. Whether in Boost or Buck mode, inductor current is a critical state variable for controllers: it serves as feedback for average-current-mode control as well as reference for cycle-by-cycle current-limit protection.

The inverter stage (H-bridge or three-level bridge arms) shares similar requirements. The grid-tied current inner loop samples output current every switching cycle, compares it with current reference, and generates PWM duty ratio via PI/PR regulators. Evidently, current sensors sit in the feedback path of all key control loops — they act as the "eyes" of the whole digital-control system.

V. Software Aspects: PWM, Sampling and Control Strategy

5.1 Evolution of PWM Mechanisms

In the IGBT era, inverters commonly deployed SPWM or SVPWM with carrier frequency of 8–16 kHz. Each switching cycle lasted 60–125 μs, leaving ample time for controllers (DSP/MCU) to complete the full workflow: sampling → filtering → PI computation → duty-ratio update.

In the SiC era, switching cycles shrink down to 10–20 μs. This brings several consequences:

• Strict synchronization between sampling and PWM: ADC sampling is triggered at peaks or valleys of triangular carriers to avoid switching-transient noise and acquire average ripple current. Higher switching frequency narrows available sampling windows and imposes stricter timing accuracy requirements.

• 1:1 binding between control cycle and switching cycle: 100 kHz switching requires full current-loop computation within every 10 μs, often demanding dual-core DSP or FPGA co-processing.

• Update-delay becomes major phase loss: digital control inherently introduces delay of ~1.5 switching cycles (sampling delay + computation delay + PWM-update delay). At higher frequencies, this delay accounts for larger proportional phase loss.

5.2 Software Current-Sensing Strategy: Dual-Channel Architecture

In real-world firmware, signals from one current sensor are processed through two functionally distinct channels:

• Control Channel (precision-prioritized): sensor analog output → RC conditioning & biasing → synchronized ADC sampling under PWM interrupt → software offset auto-calibration (using zero-crossing points of fundamental-frequency cycles or stand-still intervals), temperature compensation (interpolation according to sensor sensitivity drift coefficients), digital filtering (moving-average or notch filters suppressing switching ripple) → feeding into PI/PR computation for current loop. This channel pursues precision, linearity and low temperature drift; link delay of several microseconds is acceptable.

• Protection Channel (speed-prioritized): modern high-bandwidth sensors often provide independent fast Over-Current-Detection (OCD) comparator output pins with flexibly configurable thresholds. This pin connects directly to MCU Trip-Zone inputs or external high-speed comparators. Upon triggering, PWM outputs are hardware-latched off without software intervention; the whole "detection-to-turn-off" sequence completes within 1 μs. Software only confirms fault status afterwards and executes latch-off or auto-restart logic. This channel exists solely because SiC devices feature merely 2–3 μs short-circuit withstand time — devices would already be destroyed if waiting for software interrupt response (typically several microseconds).

Additional software considerations under high-frequency operation:

• Oversampling and multi-sample reconstruction: some schemes sample current 2–4 times within one switching cycle. Average values are extracted for control purposes while ripple-slope information is retained for online inductance identification and magnetic-component health monitoring.

• Anti-aliasing filter design: high sensor bandwidth also passes switching noise into ADC. Hardware/software filtering must carefully trade-off between preserving required loop bandwidth and avoiding sampling aliasing.

• Sensor fault self-diagnosis: read internal sensor temperature and safety status via digital interfaces (e.g. UART diagnostic port), incorporated into overall functional-safety strategy.

5.3 Bandwidth Constraints for Control Loops

Grid-tied inverters commonly adopt a double-loop structure: outer voltage / MPPT loop + inner current loop. Outer-loop bandwidth is typically only several hundred Hz, whereas inner-current-loop bandwidth is generally designed to 1/10–1/20 of switching frequency — an empirical upper bound constrained by phase margin in digital control systems.

This yields a clear causal chain:

Switching frequency fsw ↑ → current-loop bandwidth fc ↑ (fc ≈ fsw/10) → feedback-sensor bandwidth BW must exceed fc. In engineering practice BW is selected at magnitude comparable to fsw.

In other words, current-sensor bandwidth should sit in the same order of magnitude as switching frequency:

• IGBT era (fsw = 16 kHz): sensor bandwidth of 100–200 kHz suffices; traditional closed-loop Hall sensors perform adequately.

• SiC era (fsw = 50–100 kHz): bandwidth requirement rises to 500 kHz–1 MHz; conventional Hall solutions become inadequate.

VI. Why High-Bandwidth Current Sensors Are Indispensable

Insufficient sensor bandwidth creates tangible damage across three dimensions:

1. Control performance: phase lag erodes stability margin. A sensor behaves intrinsically as a low-pass element. If its bandwidth approaches control-loop bandwidth, its introduced phase lag (45° at −3 dB bandwidth) directly reduces loop phase margin. Consequences range from sluggish current dynamic response and degraded THD all the way to loop oscillation. To make sensors "nearly transparent" within control bandwidth, sensor bandwidth should be one-decade higher than loop bandwidth.

2. Protection reliability: shorter short-circuit withstand time for SiC MOSFETs. SiC MOSFET chips feature smaller die area and lower thermal capacity. Infineon CoolSiC G1/G2 specify short-circuit withstand time of 3 μs / 2 μs (compared with ~10 μs for typical IGBTs). Desaturation / overcurrent protection must complete the full "detection-comparison-turn-off" workflow within microseconds. Sensor response must reach hundreds-of-nanosecond to microsecond scale — directly translating to MHz-level bandwidth. A low-bandwidth sensor may only detect overcurrent after device destruction.

3. Measurement fidelity: loss of high-frequency-ripple information. Under high switching frequency, current ripple carries rich switching-harmonic information, valuable for magnetic-component-loss analysis, grid-harmonic evaluation and even device-health monitoring (e.g. ripple signatures indicating bond-wire degradation). Low-bandwidth sensors filter out this critical information entirely.

VII. Quantitative Relationship Between Switching Frequency and Sensor Bandwidth

Combining both control- and protection-side constraints, engineering-selection criteria can be formulated:

For a 100 kHz string inverter using Infineon CoolSiC or onsemi EliteSiC: current-loop bandwidth ≈5–10 kHz; recommended sensor bandwidth ≥1 MHz and OCD response time <1 μs. This explains the rapid market penetration of new-generation high-bandwidth current-sensing technologies: they lift bandwidth from the 100–200 kHz range of legacy solutions to hundreds of kHz up to MHz levels, while preserving galvanic isolation, high accuracy and low temperature drift. Their differential-sensing principle inherently rejects common-mode noise and stray-magnetic-field interference induced by high SiC dv/dt.

Requirements become even more stringent for SST applications. Primary- and secondary-side bridge arms within DAB isolation stages run above 100 kHz with hard-switched square-wave current. Current sensing must support phase-shift control loops while delivering microsecond-scale protection. MHz-bandwidth isolated current sensors represent practically the only viable solution.

VIII. Conclusion: Sensing Upgrade Must Keep Pace with Device Upgrade

Every device revolution in power-electronics industry redefines requirements upstream within the sensing layer. In the IGBT era, 100-kHz-class current sensors served as sufficient supporting components. In the SiC and SST era, high-bandwidth current sensors become critical devices determining control performance, protection reliability and overall unit efficiency. From the moment Infineon and onsemi pushed short-circuit withstand time down to 2–3 μs, "complete detection-and-turn-off within 1 μs" stopped being an optional bonus and became an entry-level requirement.

Switching frequency defines how fast an inverter can operate; sensor bandwidth defines whether an inverter can "see" its own operating conditions accurately. Synchronized progress between device upgrades and sensing upgrades completes the full picture for the high-frequency era.

IX. Our Solution

SiC power devices greatly boost switching frequency. Meanwhile current-sensing tasks extend beyond basic amplitude sampling. Faithful reconstruction of switching edges, current ringing and high-frequency ripple directly influences inverter-control stability, loss-calculation accuracy, and protection-response speed for multi-port bidirectional SST conversion.

Giant-Magneto-Resistance (GMR) provides graded-bandwidth product portfolios for diverse operating-condition scenarios, covering 200 kHz, 400 kHz up to 1 MHz. From regular control sampling to capturing high-frequency transients, these offerings flexibly match development-debugging, unit-validation and long-term operational monitoring requirements for SiC PV inverters and SST solid-state transformers. They deliver high-performance domestic current-sensing alternatives for new-generation digital-energy equipment.